Since I don’t know a whole lot about timing signals, if the BOE is using less bandwidth, does it somehow have a lesser picture quality? If the quality is the same, why would the SDC panel require more bandwidth to display the exact same picture?
Signal padding, there happen to be empty/blank pixels sent which make things easier for display controllers when detecting timings, historically those blank pixels were there to give time for CRT electron beams to move to where the next line or frame began.
For BOE panels at 90hz, they receive frames which happen to be 858x1320 pixels in size, with an active area of 800x1280, while SDC panels use frames which are 1128x1312 in size, also with an 800x1280 active area.
So…
for BOE: 858x1320x90 = 101930400; ie a clock of ~101.93MHz; though in reality the panel runs at 102mhz so has a refresh rate of ~90.0615Hz.
and for SDC: 1128x1312x90 = 133194240; so a clock of 133.194mhz; but they run at 133.200MHz instead which gives a refresh rate of ~90.004Hz
Reducing how large of a padding area gets sent may be possible, but without having an SDC panel deck myself I’m not able to test to which degree, if any, that would be possible.
Thanks for the detailed answer, that makes more sense! So it all comes down to the controller and how much padding it needs to make sure it has the right pixels in the right area of the screen. Depending on the speed/sensitivity of the controller, it determines how much extra padding or bandwidth is used to make the same picture. That makes sense on a CRT due to the physical limitation of an electron gun only being able to move so fast. I’m surprised that some modern day controller chips would need so much extra padding!
Since I don’t know a whole lot about timing signals, if the BOE is using less bandwidth, does it somehow have a lesser picture quality? If the quality is the same, why would the SDC panel require more bandwidth to display the exact same picture?
Signal padding, there happen to be empty/blank pixels sent which make things easier for display controllers when detecting timings, historically those blank pixels were there to give time for CRT electron beams to move to where the next line or frame began.
For BOE panels at 90hz, they receive frames which happen to be 858x1320 pixels in size, with an active area of 800x1280, while SDC panels use frames which are 1128x1312 in size, also with an 800x1280 active area.
So…
for BOE: 858x1320x90 = 101930400; ie a clock of ~101.93MHz; though in reality the panel runs at 102mhz so has a refresh rate of ~90.0615Hz.
and for SDC: 1128x1312x90 = 133194240; so a clock of 133.194mhz; but they run at 133.200MHz instead which gives a refresh rate of ~90.004Hz
Reducing how large of a padding area gets sent may be possible, but without having an SDC panel deck myself I’m not able to test to which degree, if any, that would be possible.
Thanks for the detailed answer, that makes more sense! So it all comes down to the controller and how much padding it needs to make sure it has the right pixels in the right area of the screen. Depending on the speed/sensitivity of the controller, it determines how much extra padding or bandwidth is used to make the same picture. That makes sense on a CRT due to the physical limitation of an electron gun only being able to move so fast. I’m surprised that some modern day controller chips would need so much extra padding!